Computing systems generally rely on memory devices to store information. Such memory devices may be divided into two general types. First, volatile memory devices which require power to maintain correctness of the stored information. Second, non-volatile memory devices which maintain the stored information even after power is cut off.
One common type of volatile memory device is Dynamic Random Access Memory (DRAM). DRAM devices generally provide significantly improved performance over mechanical storage devices (such as hard disks), while providing lower cost than Static Random Access Memory (SRAM) devices.
DRAMs generally store each bit of data in a separate capacitor within an integrated circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement and other design considerations, DRAMs designers impose various timing constraints on operations within a DRAM to maintain correctness. One such constraint is a precharge requirement. In particular, when access is requested to a different row (also referred to as a Bit Line (BL)) in a DRAM, the current row has to be first deactivated by issuing a “precharge” command. The precharge command will cause the sense amplifiers to switch off and the bit lines to be precharged to matching voltages that are intermediate between high and low logic levels. After a certain row precharge time period delay (also referred to as tRP), an “activate” command may be issued to activate the next row to be accessed.
Current DRAMs, however, allow no access concurrency to different banks in the DRAM after a precharge command is issued. In particular, a single timing value is used to cover precharge operation for the entire DRAM device. And, an “activate” command to open a row of memory in the DRAM device may only be issued after a delay of tRP from any precharge command.